1. Field
Example embodiments relate to semiconductor memory devices and methods for fabricating semiconductor memory devices. Also, example embodiments relate to nonvolatile memory devices with increased threshold voltage windows and methods for fabricating nonvolatile memory devices with increased threshold voltage windows.
2. Description of Related Art
Nonvolatile memory devices may be semiconductor memory devices that may retain the stored data even when not powered. A typical example of nonvolatile memory devices may be a flash memory device. A cell transistor of the flash memory device may have a charge storage layer interposed between a control gate and a semiconductor substrate, and/or the threshold voltage of the cell transistor may change depending on the quantity of charge stored in the charge storage layer. The flash memory device may use a threshold voltage difference, that may depend on the charge quantity of the charge storage layer, to discriminate the stored data.
As well known in the art, flash memory devices may be classified into a floating gate type and a charge trap type according to the structure of the charge storage layer. As the degree of integration increases, the floating gate flash memory device may be vulnerable to the problems of the inter-cell interference and/or the aspect ratio of a cell gate pattern. Therefore, the floating gate flash memory device may have a limitation in satisfying a commercial demand for high integration. The charge trap flash (CTF) memory device may use a thin layer with abundant trap sites as the charge storage layer. Therefore, the CTF memory device may have the advantages of requiring a simpler fabrication process and/or of having a lower cell gate pattern than a floating gate memory device using polycrystalline silicon.
A typical CTF memory device may have a tunnel insulating layer, a charge storage layer, a blocking insulating layer, and/or a control gate that may be sequentially stacked on a semiconductor substrate. Charges causing a threshold voltage difference may be charged/discharged into/from the charge storage layer, and/or the charge/discharge operation may be performed using a charge tunneling phenomenon in the tunnel insulating layer. The charge tunneling phenomenon may be controlled using a voltage applied to the control gate.
The voltage applied to the control gate may cause a back-tunneling phenomenon in which charges stored in the charge storage layer tunnel the blocking insulating layer and/or leak into the control gate. In order to reduce the back-tunneling phenomenon, a recently-proposed typical TANOS flash memory device may use an aluminum oxide layer and/or a tantalum nitride layer as a blocking insulating layer and/or a control gate, respectively. However, the typical TANOS flash memory device may have a limitation in implementing a multi-level cell (MLC) that has been recently proposed for high integration.
The MLC technology may be used to store multi-bit data in a single memory cell. To this end, a threshold voltage window, that may be defined as a threshold voltage difference between a program state and an erase state, may be required to be wide. In this context, the quantity Q of charge stored in a charge storage layer may be defined as the product of the capacitance C of a blocking insulating layer and a threshold voltage window ΔVT (i.e., Q=CΔVT). Thus, when the charge quantity Q of the charge storage layer is constant, an increase in the capacitance C of the blocking insulating layer may cause a decrease in the threshold voltage window ΔVT.
However, since the aluminum oxide layer used as the blocking insulating layer may have a high permittivity, it may be difficult to increase the threshold voltage window of the typical TANOS flash memory device.